In an article entitled: "Charge-Coupled Devices-A New Approach to MIS Device Sructure" IEEE Spectrum, July 1971, pp 18-27; W. S. Boyle and G. E. Smith describe a new information-handling structure, the charge coupled device (CCD). The device, which may be of the metal-oxide-semiconductor (MOS) type, stores a minority-carrier charge in potential wells created at the surface of a semiconductor and transports the charge along the surface by the application of bias potentials to move the potential wells. The charge tends to decay after a relatively short period of time due to thermal effects and consequently must be periodically regenerated by known means. In addition to the semiconductor type utilizing minority-carrier charge transport, CCDs have also been constructed using a semi-insulating material where the charge transport is via majority carriers.
An important consideration of any CCD is the storage efficiency. In a conventional two-phase CCD, two storage electrodes are required per bit, in a three-phase device three storage electrodes are required, in a four-phase device again two storage electrodes are required per bit. Such structures are rather inefficient in terms of storage capacity yielding a maximum of only 50% for a two-phase device. In a paper entitled: "CCD Memory Options" by D. R. Collins, J. B. Barton, D. C. Buss, A. R. Kmetz and J. E. Schroeder, 1973 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, pp 136 et seq; FIG. 4 illustrates an alternate approach. Here, there is shown the conceptual organization of a full-ripple CCD in which charges are stored beneath all but one of the electrodes. Each charge in turn is sequentially transferred in ripple fashion into an adjacent empty location which thus propagates in the opposite direction to the flow of charges along the device. However, a realizable structure of this concept raises severe problems. Since only one charge transfer can take place at any one instant in time, a CCD with a storage capacity of n-bits must be driven by an (n+1) phase clock. In large storage capacity CCDs (i.e. those containing upwards of 100 storage elements) this virtually rules out the use of a multi-phased clock which is individually coupled to each field plate utilizing separate conductive drive lines, due to the complexity of such a structure as well as the clock itself. An alternate solution would be to drive the CCD chain utlizing a (n+1) bit FET shift register which is connected in parallel with the CCD. However such an arrangement also requires that an individual, separate connection be made to each storage electrode, is costly in terms of space and increases the complexity of the transistor circuitry forming part of the overall device.
Typically, in a two-level CCD the field plates of each level measure 8.mu.m in the direction of charge flow separated by a gap between adjacent electrodes of 4.mu.m thus yielding a 2.mu.m overlap on each side of the upper and lower levels. If a structure of these dimensions is to be used as a multi-ripple device, it is necessary to bond the ends of each of the field plates to different conductive drive lines which couple the clock voltages to the device. However, at the present state of the art, these dimensions are too small to insure sufficient overlap of the bonding areas and hence it is necessary to provide contact pads having almost twice the width (typically 14.mu.m) of the field plates. However, because of the width and close spacing between the electrode plates, these pads introduce additional structural problems in the realization of a practical design, in view of their size and the limited width available between plates.